1. Field of the Invention
The present invention relates to an electrostatic discharge immunizing circuit, and more particularly, to an electrostatic discharge immunizing circuit without area penalty.
2. Description of the Prior Art
In a conventional chip, since the size of the chip is small, and both the operating voltage and the operating current are small also, switches of voltage levels of elements of a core circuit, which is responsible for calculations of the chip, have to be extremely precise. However, since the chip is conventionally disposed around electronic devices for reducing the volume of an electronic product, the core circuit in the chip is vulnerable to electrostatic discharges released by the electronic devices, and thus easily leads to miscalculations. For preventing the core circuit from being affected by the electrostatic discharges, an electrostatic discharge immunizing circuit (ESD immunizing circuit) is conventionally disposed in the chip for discharging the released electrostatic discharges by providing discharging paths for the released electrostatic discharges so that the calculations of the core circuit are protected. In principle, the core circuit is disposed at the center of the chip, and the ESD immunizing circuit is disposed at surroundings of the chip in the prior art. Therefore, the ESD immunizing circuit may be as far away from the core circuit as possible for preventing electrostatic discharges from getting close to the core circuit, and for guiding the electrostatic discharges to be discharged. However, when the core circuit is implemented with analog circuits, since the volume of the core circuit is small, the core circuit of the prior art is sensitive to the released electrostatic discharges, analog I/O signals of the core circuit are affected, and erroneous calculations of the chip are thus generated. For neutralizing such defects, there are several chips in the prior art that are provided for completely discharging the released electrostatic discharges by adding additional ESD immunizing circuits around the provided chips. However, these additional ESD immunizing circuits lead to larger area penalties of the provided chip of the prior art so that these additional ESD immunizing circuits are not economical solutions for neutralizing such defects.